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21143 PCI/CardBus 10/100 Ethernet LAN Controller
Networking Silicon
Preliminary Datasheet
Product Features
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Fully compliant with Revision 2.1 of the PCI Local Bus Specification and with Revision 1.0 of the PCI Bus Power Management Interface Specification. Fully compliant with Revision 1.0 of the Advanced Configuration and Power Interface (ACPI) Specification and with Revision 1.0 of the Network Device Class Power Management Specification, under the OnNow Architecture for Microsoft's PC 97 Hardware Design Guide and PC 98 System Design Guide. Supports IEEE 802.3 with full Auto-Negotiation algorithm of full-duplex and half-duplex operation for 10 Mb/s and 100 Mb/s (NWAY). Supports IEEE 802.3 and ANSI 8802-3 Ethernet standards. Supports direct memory access (DMA) and has direct interface to both the CardBus* and PCI local bus. Provides glueless 32-bit PCI bus master interface.
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Contains large independent receive and transmit FIFOs. Contains internal PCS and scrambler/ descrambler for MII/SYM interface for 100BASE-TX. Contains onchip integrated AUI port and a 10BASE-T transceiver. Supports autodetection between 10BASE-T, AUI, and MII/SYM ports. Provides an upgradable boot ROM interface up to 256KB. Supports remote wake-up-LAN and Magic Packet* with the SecureONTM password option. Supports PCI/CardBus clock speed frequency from dc to 33 MHz; network operation with PCI clock from 20 MHz to 33 MHz. Implements low-power management with two power-saving modes (sleep and snooze). Implements low-power, 3.3-V CMOS technology.
Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 278073-001 November 1998
21143
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 21143 PCI/CardBus 10/100 Ethernet LAN Controller may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright (c) Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners.
Preliminary Datasheet
21143
Contents
1.0 21143 OVERVIEW .......................................................................................................................... 1 1.1 1.2 2.0 2.1 2.2 2.3 2.4 3.0 3.1 3.2 3.3 3.4 General Description ............................................................................................................ 2 Microarchitecture ................................................................................................................ 3 Signal Reference Tables .................................................................................................... 7 Signal Reference Tables .................................................................................................... 9 Pin Tables.........................................................................................................................15 Signal Grouping by Function ............................................................................................17 Voltage Limit Ratings........................................................................................................19 Temperature Limit Ratings ...............................................................................................19 Power Specifications ........................................................................................................ 20 PCI Bus and CardBus Electrical Parameters ...................................................................20 3.4.1 PCI and CardBus I/O Voltage Specifications ...................................................21 3.4.2 System Bus Reset ............................................................................................22 3.4.3 PCI and CardBus Clock Specifications ............................................................22 3.4.4 Other PCI and CardBus Signals.......................................................................24 AUI and Twisted-Pair DC Specifications ..........................................................................25 Serial Interface Attachment Specifications .......................................................................26 3.6.1 Serial Clock Timing ..........................................................................................26 3.6.2 Internal SIA Mode AUI Timing--Transmit ........................................................27 3.6.3 Internal SIA Mode AUI Timing--Receive .........................................................28 3.6.4 Internal SIA Mode AUI Timing--Collision.........................................................28 3.6.5 Internal SIA Mode 10BASE-T Interface Timing--Transmit ..............................29 3.6.6 Internal SIA Mode 10BASE-T Interface Timing--Receive ...............................30 3.6.7 Internal SIA Mode 10BASE-T Interface Timing--Idle Link Pulse .....................31 MII Interface Specifications ..............................................................................................32 MII/SYM Port Timing ........................................................................................................32 3.8.1 MII/SYM 10/100-Mb/s and 10-Mb/s Timing--Transmit ....................................32 3.8.2 MII/SYM 10/100-Mb/s Timing--Receive ..........................................................34 3.8.3 SYM 10/100-Mb/s Timing--Signal Detect ........................................................35 3.8.4 MII 10/100-Mb/s Timing--Receive Error ..........................................................35 3.8.5 MII 10/100-Mb/s Timing--Carrier Sense and Collision ....................................36 Boot ROM and Serial ROM Port Specification .................................................................36 Boot ROM Port Timing .....................................................................................................37 3.10.1 Boot ROM Read Timing ...................................................................................37 3.10.2 Boot ROM Write Timing....................................................................................38 Serial ROM Port Timing....................................................................................................39 External Register Timing ..................................................................................................39 Joint Test Action Group--Test Access Port .....................................................................41 3.13.1 JTAG DC Specifications ...................................................................................41 3.13.2 JTAG Boundary-Scan Timing...........................................................................42
PINOUT ........................................................................................................................................... 5
ELECTRICAL AND ENVIRONMENTAL SPECIFICATIONS........................................................19
3.5 3.6
3.7 3.8
3.9 3.10
3.11 3.12 3.13
4.0
MECHANICAL SPECIFICATIONS ...............................................................................................43
Preliminary Datasheet
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21143
1.0
21143 Overview
The Intel 21143 PCI/CardBus* 10/100-Mb/s Ethernet LAN Controller (21143) supports the peripheral component interconnect (PCI) bus or CardBus. It provides a direct interface connection to the PCI bus and adapts easily to the CardBus and most other standard buses. The 21143 software interface and data structures are optimized to minimize the host CPU load and to allow for maximum flexibility in the buffer descriptor management. The 21143 contains large onchip FIFOs, so no additional onboard memory is required. The 21143 also provides an upgradable boot ROM interface. In addition to the features listed on the title pages, the following features are also supported by the 21143: PCI and CardBus Features:
* * * *
Supports PCI and CardBus interfaces. Supports PCI/CardBus clock control through clkrun. Supports CardBus cstschg pin and Status Changed registers. Supports automatic loading of subvendor ID and CardBus card information structure (CIS) pointer from serial ROM to configuration registers. expansion ROM.
* Supports storage of CardBus card information structure (CIS) in the serial ROM or the * Supports the advanced PCI/CardBus read multiple, read line, and write and invalidate
commands.
* Supports an unlimited PCI/CardBus burst.
Host Interface Features:
* Includes a powerful onchip direct memory access (DMA) with programmable burst size,
providing low CPU utilization.
* * * *
Supports early interrupt on transmit and receive. Supports interrupt mitigation on transmit and receive. Supports big or little endian byte ordering for buffers and descriptors. Implements unique, patented intelligent arbitration between DMA channels to minimize underflow and overflow.
* Contains large independent receive and transmit FIFOs.
Network Side Features:
* Supports three network ports: 10BASE-T (10 Mb/s), AUI (10 Mb/s), and
MII/SYM (10/100 Mb/s).
* Contains a variety of flexible address filtering modes. * Implements signal-detect filtering to avoid false detection of link with 100BASE-TX symbol
interfaces.
* Enables automatic detection and correction of 10BASE-T receive polarity. * Supports autodetection between 10BASE-T, AUI, and MII/SYM ports. * Offers a unique, patented solution to Ethernet capture-effect problem.
Preliminary Datasheet
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21143
* Supports full-duplex operation on both MII/SYM and 10BASE-T ports. * Provides internal and external loopback capability on all network ports. * Supports IEEE 802.3 and ANSI 8802-3 Ethernet standards.
Other Features:
* * * *
Provides MicroWire* interface for serial ROM (1K and 4K EEPROM). Provides LED indications for various network activity. Implements test-access port (JTAG-compatible) with boundary-scan pins. Contains a 4-bit, general-purpose programmable register and corresponding I/O pins with the ability to generate interrupts from two general-purpose pins.
1.1
General Description
The 21143 is an Ethernet LAN controller for both 100-Mb/s and 10-Mb/s data rates, which provides a direct interface to the peripheral component interconnect (PCI) local bus or the CardBus. The 21143 interfaces to the host processor by using onchip command and status registers (CSRs) and a shared host memory area, set up mainly during initialization. This minimizes processor involvement in the 21143 operation during normal reception and transmission. The 21143 is optimized for low power PCI/CardBus based systems and supports two types of power-management mechanisms. The main mechanism is based upon the OnNow architecture, which is required for PC 97 and PC 98. The alternative mechanism is based upon the older remote wake-up-LAN mechanism. Large FIFOs allow the 21143 to efficiently operate in systems with longer latency periods. Bus traffic is also minimized by filtering out received runt frames and by automatically retransmitting collided frames without a repeated fetch from the host memory. The 21143 provides three network ports: a 10BASE-T 10-Mb/s port, an attachment unit interface (AUI) 10-Mb/s port, and a media-independent/symbol interface (MII/SYM) 10/100-Mb/s port. The 10BASE-T port provides a direct Ethernet connection to the twisted-pair (TP) interface. The AUI port provides a direct Ethernet connection to the AUI. The MII/SYM port supports two operational modes:
* MII mode--A full implementation of the MII standard * SYM mode--Symbol interface to an external 100-Mb/s front-end decoder (ENDEC). In this
mode the 21143 uses an onchip physical coding sublayer (PCS) and a scrambler/descrambler circuit to enable a low-cost 100BASE-T implementation. The 21143 is capable of functioning in a full-duplex environment for the MII/SYM and 10BASE-T ports. The 21143 provides an upgradable boot ROM interface.
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Preliminary Datasheet
21143
1.2
Microarchitecture
The following list describes the 21143 hardware components, and Figure 1 shows a block diagram of the 21143:
* PCI/CardBus interface--Includes all interface functions to the PCI and CardBus bus; handles
all interconnect control signals; and executes DMA and I/O transactions
* Boot ROM port--Provides an interface to perform read and write operations to the boot ROM;
supports accesses to bytes or longwords (32-bit); and provides the ability to connect an external 8-bit register to the boot ROM port
* Serial ROM port--Provides a direct interface to a MicroWire ROM for storage of the Ethernet
address and system parameters
* General-purpose register--Enables software use for input or output functions and LEDs * DMA--Contains independent receive and transmit controllers; handles data transfers between
CPU memory and onchip memory
* FIFOs--Contains independent FIFOs for receive and transmit; supports automatic packet
deletion on receive (runt packets or after a collision) and packet retransmission after a collision on transmit
* TxM--Handles all CSMA/CD1 MAC2 transmit operations, and transfers data from transmit
FIFO to the ENDEC for transmission
* RxM--Handles all CSMA/CD MAC receive operations, and transfers the network data from
the ENDEC to the receive FIFO
* SIA interface--Performs 10-Mb/s physical layer network operations; implements the AUI and
10BASE-T functions, including the Manchester encoder and decoder functions
* NWAY--Implements the IEEE 802.3 Auto-Negotiation algorithm * Physical coding sublayer--Implements the encoding and decoding sublayer of the
100BASE-TX (CAT5) specification, including the squelch feature
* Scrambler/descrambler--Implements the twisted-pair physical layer medium dependent
(TP-PMD) scrambler/descrambler scheme for 100BASE-TX
* Three network interfaces--An AUI interface, a 10BASE-T interface, and an MII/SYM
interface provide a full MII signal interface and direct interface to the 100-Mb/s ENDEC for CAT5
* Wake-up-controller--Enables power-management control compliant with the ACPI and
remote power-up capabilities using the remote wake-up-LAN mechanism
1. Carrier-sense multiple access with collision detection. 2. Media access control.
Preliminary Datasheet
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21143
PCI/CardBus
Board Control and LEDs
Serial ROM
Boot ROM/ External Register
PCI/CardBus Interface 32 DMA 32
GeneralPurpose Register 4
Serial ROM Port 32 32
Boot ROM Port 32
Rx FIFO
Tx FIFO 16
16 RxM Wake-Up Controller
TxM
1
4 4 1 Physical Coding Sublayer (PCS)
SIA Interface
NWAY 4 Scrambler/ Descrambler 4
AUI Interface
10BASE-T Interface
MII/SYM Interface
10 Mb/s
10 Mb/s
10/100 Mb/s
FM-06117.AI4
Figure 1. 21143 Block Diagram
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Preliminary Datasheet
21143
2.0
Pinout
The 21143 is offered in two package styles: a 144-pin low-profile quad flat pack (LQFP) and a 144-pin metric quad flat pack (MQFP). The tables in this section provide a description of the pins and their respective signal definitions. Table 1 lists the tables in this section. Figure 2 shows the 21143 pinout for both the LQFP and MQFP package types Table 1. Index to Pinout Tables
For this information... Logic signals Power pins Functional signals description Input pins Output pins Input/output pins Open drain pins Signal functions Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Refer to...
Preliminary Datasheet
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21143
vdd vdd vss tp_td-tp_tdtp_td+ tp_td++ vdd tp_rd+ tp_rdtck tms tdi tdo int_l rst_l vss vdd pci_clk vdd_clamp gnt_l req_l ad<31> ad<30> ad<29> vdd ad<28> ad<27> ad<26> vss ad<25> ad<24> c_be_l<3> idsel vss vdd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
vss aui_tdaui_td+ vdd aui_rdaui_rd+ aui_cdaui_cd+ vdd mii_mdio mii_mdc mii/sym_rxd<3> mii/sym_rxd<2> mii/sym_rxd<1> mii/sym_rxd<0> mii_dv mii/sym_rclk mii_rx_err/sel10_100 vss vdd mii/sym_tclk mii_txen/sym_txd<4> mii/sym_txd<0> mii/sym_txd<1> mii/sym_txd<2> mii/sym_txd<3> mii_clsn/sym_rxd<4> mii_crs/sd vss sr_cs sr_ck sr_di sr_do vddac vcap_h vddac 111111111111111111111111111111111111 444443333333333222222222211111111110 432109876543210987654321098765432109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 iref vdd xtal1 xtal2 vss gep<3>/link gep<2>/rcv_match/wake gep<1>/activ gep<0>/aui_bnc br_ad<7> br_ad<6> br_ad<5> br_ad<4> vdd vss br_ad<3> br_ad<2> br_ad<1> br_ad<0> br_a<1> br_a<0>/cb_pads_l br_ce_l clkrun_l ad<0> ad<1> vss ad<2> ad<3> ad<4> vdd ad<5> ad<6> ad<7> c_be_l<0> vss vdd
21143
333444444444455555555556666666666777 789012345678901234567890123456789012 vdd vss ad<23> ad<22> ad<21> vss ad<20> ad<19> ad<18> vdd ad<17> ad<16> c_be_l<2> frame_l irdy_l trdy_l vss vdd devsel_l stop_l perr_l serr_l par c_be_l<1> ad<15> ad<14> vss ad<13> ad<12> ad<11> vdd ad<10> ad<9> ad<8> vss vdd
A5992-01
Figure 2. 21143 Pinout Diagram (Top View)
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Preliminary Datasheet
21143
2.1
Signal Reference Tables
Table 2 provides an alphabetical list of the 21143 logic names and their pin numbers. Table 3 provides a list of the 21143 power pin numbers.
Preliminary Datasheet
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21143
.
Table 2. Logic Signals (Sheet 1 of 2)
Signal ad<0> ad<1> ad<2> ad<3> ad<4> ad<5> ad<6> ad<7> ad<8> ad<9> ad<10> ad<11> ad<12> ad<13> ad<14> ad<15> ad<16> ad<17> ad<18> ad<19> ad<20> ad<21> ad<22> ad<23> ad<24> ad<25> ad<26> ad<27> ad<28> ad<29> ad<30> ad<31> aui_cd- aui_cd+ Pin Number 85 84 82 81 80 78 77 76 70 69 68 66 65 64 62 61 48 47 45 44 43 41 40 39 32 31 29 28 27 25 24 23 138 137 Signal aui_rd- aui_rd+ aui_td- aui_td+ br_a<0>/ cb_pads_l br_a<1> br_ad<0> br_ad<1> br_ad<2> br_ad<3> br_ad<4> br_ad<5> br_ad<6> br_ad<7> br_ce_l c_be_l<0> c_be_l<1> c_be_l<2> c_be_l<3> clkrun_l devsel_l frame_l gep<0>/ aui_bnc gep<1>/activ gep<2>/ rcv_match/ wake gep<3>/link gnt_l idsel int_l irdy_l iref mii_clsn/ sym_rxd<4> mii_crs/sd mii_dv Pin Number 140 139 143 142 88 89 90 91 92 93 96 97 98 99 87 75 60 49 33 86 55 50 100 101 102 103 21 34 15 51 108 118 117 129 mii_mdc mii_mdio mii/sym_rclk mii_rx_err/sel10_100 mii/sym_rxd<0> mii/sym_rxd<1> mii/sym_rxd<2> mii/sym_rxd<3> mii/sym_tclk mii/sym_txd<0> mii/sym_txd<1> mii/sym_txd<2> mii/sym_txd<3> mii_txen/sym_txd<4> par pci_clk perr_l req_l rst_l serr_l sr_ck sr_cs sr_di sr_do stop_l tck tdi tdo tms tp_rd- tp_rd+ tp_td- tp_td- - tp_td+ Signal Pin Number 134 135 128 127 130 131 132 133 124 122 121 120 119 123 59 19 57 22 16 58 114 115 113 112 56 11 13 14 12 10 9 5 4 6
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Preliminary Datasheet
21143
Table 2. Logic Signals (Sheet 2 of 2)
Signal tp_td+ + xtal1 Pin Number 7 106 Signal trdy_l xtal2 Pin Number 52 105 vcap_h -- Signal Pin Number 110 --
Table 3. Power Pins
Signal Pin Number 1, 2, 8, 18, 26, 36, 37, 46, 54, 67, 72, 73, 79, 95, 107, 125, 136, 141 109, 111 20 Signal Pin Number 3, 17, 30, 35, 38, 42, 53, 63, 71, 74, 83, 94, 104, 116, 126, 144 -- --
vdd (3.3 V)
vss (GND)
vddac (3.3 V) vdd_clamp (5 V or 3.3 V)
-- --
2.2
Signal Reference Tables
The functional grouping of each pin is listed in Section 2.4. The following terms describe the 21143 pinout:
* Address phase
Address and appropriate bus commands are driven during this cycle.
* Data phase
Data and the appropriate byte enable codes are driven during this cycle.
* _l
All pin names with the _l suffix are asserted low. The following pins in Table 4 have an internal pull-up: tms tdi br_ce_l sr_do mii/sym_tclk Pin sr_cs has an internal pull-down. Table 4 uses the following abbreviations: I = Input O = Output I/O = Input/output O/D = Open drain P = Power
Preliminary Datasheet
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21143
Table 4 provides a functional description of each of the 21143 signals. These signals are listed alphabetically. Table 4. Functional Description of 21143 Signals (Sheet 1 of 6)
Signal Type Pin Number 23, 24, 25, 27, 28, 29, 31, 32, 39, 40, 41, 43, 44, 45, 47, 48, 61, 62, 64, 65, 66, 68, 69, 70, 76, 77, 78, 80, 81, 82, 84, 85 138 137 140 139 143 142 Description 32-bit PCI address and data lines. Address and data bits are multiplexed on the same pins. During the first clock cycle of a transaction, the address bits contain a physical address (32 bits). During subsequent clock cycles, these same lines contain 32 bits of data. A 21143 bus transaction consists of an address phase followed by one or more data phases. The 21143 supports both read and write bursts (in master operation only). Little and big endian byte ordering can be used. Attachment unit interface receive collision differential negative data. Attachment unit interface receive collision differential positive data. Attachment unit interface receive differential negative data. Attachment unit interface receive differential positive data. Attachment unit interface transmit differential negative data. Attachment unit interface transmit differential positive data. Boot ROM address line bit 0. In a 256KB configuration, this pin also carries in two consecutive address cycles, boot ROM address bits 16 and 17. O 88 This pin also determines the type of signals to use for the PCI/ CardBus* output pins, either PCI or CardBus. By default, this pin selects PCI signaling. To select CardBus signaling, this pin must be connected to a pull-down resistor. Boot ROM address line bit 1. This pin also latches the boot ROM address and control lines by the two external latches. Boot ROM address and data multiplexed lines bits 7 through 0. In two consecutive address cycles, these lines contain the boot ROM address pins 7 through 2, oe_l and we_l in the first cycle; and these lines contain boot ROM address pins 15 through 8 in the second cycle. During the data cycle, bits 7 through 0 contain data. Boot ROM or external register chip enable. Bits 0 through 3 of the bus command and byte enable lines. Bus command and byte enable are multiplexed on the same PCI pins. c_be_l<3:0> I/O 33, 49, 60, 75 During the address phase of the transaction, these 4 bits provide the bus command. During the data phase, these 4 bits provide the byte enable. The byte enable determines which byte lines carry valid data. For example, bit 0 applies to byte 0, and bit 3 applies to byte 3. PCI/CardBus clock run indication. The host system asserts this signal to indicate normal operation of the clock. The host system deasserts clkrun_l when the clock is going to be stopped or slowed down to a nonoperational frequency. 86 If the clock is needed by the 21143, the 21143 asserts clkrun_l, requesting normal clock operation to be maintained or restored. Otherwise, the 21143 allows the system to stop the clock. If this pin is not connected to the PCI/CardBus bus, it should be connected to a pull-down resistor.
ad<31:0>
I/O
aui_cd- aui_cd+ aui_rd- aui_rd+ aui_td- aui_td+
I I I I O O
br_a<0>/ cb_pads_l
br_a<1>
O
89
br_ad<7:0>
I/O
90, 91, 92, 93, 96, 97, 98, 99
br_ce_l
O
87
clkrun_l
I/O O/D
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Preliminary Datasheet
21143
Table 4. Functional Description of 21143 Signals (Sheet 2 of 6)
Signal Type Pin Number Description Device select is asserted by the target of the current bus access. When the 21143 is the initiator of the current bus access, it expects the target to assert devsel_l within 5 bus cycles, confirming the access. If the target does not assert devsel_l within the required bus cycles, the 21143 aborts the cycle. To meet the timing requirements, the 21143 asserts this signal in a medium speed (within 2 bus cycles). The frame_l signal is driven by the bus master to indicate the beginning and duration of an access. The frame_l signal asserts to indicate the beginning of a bus transaction. While frame_l is asserted, data transfers continue. The frame_l signal deasserts to indicate that the next data phase is the final data phase transaction. This pin can be configured by software to be: * A general-purpose pin that performs either input or output functions. This general-purpose pin can provide an interrupt when functioning as an input. gep<0>/ aui_bnc I/O 100 * A control pin that provides an AUI (10BASE5) or BNC (10BASE2) select line. This control pin is mainly used to enable the external BNC transceiver in 10BASE2 mode. When set, the 10BASE5 mode is selected. When reset, the 10BASE2 mode is selected. NOTE: This control pin is internally forced to the aui_bnc function when the 21143 is in remote wake-up-LAN mode. This pin can be configured by software to be: gep<1>/activ I/O 101 * A general-purpose pin that performs either input or output functions. This general-purpose pin can provide an interrupt when functioning as an input. * A status pin that provides an LED that indicates either receive or transmit activity. This pin can be configured by software to be: * A general-purpose pin that performs either input or output functions. * A status pin that provides an LED that indicates a receive packet has passed address recognition. gep<2>/ rcv_match/ wake I/O 102 If the PME_Enable bit (Func0_HwOptions<3>) in the serial ROM is set, this pin is forced to function as a wake-up event pin that can be connected to pin pme# of the PCI connector or pin cstschg of the CardBus connector. When the 21143 is in remote wake-up-LAN mode, this pin is used as an indicator that a Magic Packet* has been successfully detected. When this pin is in a wake function, bit MiscHwOptions<1> in the serial ROM determines the polarity. The PME function takes precedence over the Magic Packet indication function. This pin can be configured by software to be: * A general-purpose pin that performs either input or output functions. When configured as an input pin in OnNow mode, this pin functions as link status. When used with an MII PHY device, this pin should be connected to the MII PHY link indication pin (the 21143 interprets link-pass when this pin is high). This pin should not be left unconnected if it is configured as an input in D1, D2 or D3 power states. * A status pin that provides an LED to indicate: -Network link integrity state for 10BASE-T or 100BASE-TX if Func1_Hw_Options<8> is cleared in the SROM. -Both network activity and network link integrity state if Func1_Hw_Options<8> is set in the SROM.
devsel_l
I/O
55
frame_l
I/O
50
gep<3>/link
I/O
103
Preliminary Datasheet
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21143
Table 4. Functional Description of 21143 Signals (Sheet 3 of 6)
Signal gnt_l idsel Type I I Pin Number 21 34 Description Bus grant asserts to indicate to the 21143 that access to the bus is granted. Initialization device select asserts to indicate that the host is issuing a configuration cycle to the 21143. Interrupt request asserts when one of the appropriate bits of CSR5 sets and causes an interrupt, provided that the corresponding mask bit in CSR7 is not asserted. Interrupt request deasserts by writing a 1 into the appropriate CSR5 bit. If more than one interrupt bit is asserted in CSR5 and the host does not clear all input bits, the 21143 deasserts int_l for one cycle to support edge-triggered systems. iref I 108 Current reference input for the analog phase-locked loop logic. Initiator ready indicates the bus master's ability to complete the current data phase of the transaction. A data phase is completed on any rising edge of the clock when both irdy_l and target ready trdy_l are asserted. Wait cycles are inserted until both irdy_l and trdy_l are asserted together. When the 21143 is the bus master, it asserts irdy_l during write operations to indicate that valid data is present on the 32-bit ad lines. During read operations, the 21143 asserts irdy_l to indicate that it is ready to accept data. In MII mode (CSR6<18>=1, CSR6<23>=0), this pin functions as the collision detect. When the external physical layer protocol (PHY) device detects a collision, it asserts this pin. mii_clsn/ sym_rxd<4> I 118 In SYM mode (CSR6<18>=1, CSR6<23>=1), this pin functions as receive data. This line along with the four receive lines (sym_rxd<3:0>) provides five parallel data lines in symbol form. This data is controlled by an external physical layer medium-dependent (PMD) device and should be synchronized to the sym_rclk signal. In MII mode this pin functions as the carrier sense and is asserted by the PHY when the media is active. In SYM mode this pin functions as the signal detect indication. It is controlled by an external PMD device. Data valid is asserted by an external PHY when receive data is present on the mii_rxd lines and is deasserted at the end of the packet. This signal should be synchronized with the mii_rclk signal. MII management data clock is sourced by the 21143 to the PHY devices as a timing reference for the transfer of information on the mii_mdio signal. MII management data input/output transfers control information and status between the PHY and the 21143. Supports either the 25-MHz or 2.5-MHz receive clock. This clock is recovered by the PHY. When used with an MII PHY device (CSR6<18>=1, CSR6<23>=0), this pin functions as receive error input. It is asserted when a data decoding error is detected by an external PHY device. This signal is synchronized to mii_rclk and can be asserted for a minimum of one receive clock. When asserted during a packet reception, it sets the cyclic redundancy check (CRC) error bit in the receive descriptor (RDES0). When used with a SYM PHY device (CSR6<23>=1), this pin functions as select 10/100 output. The signal sel10_100 equals 1 when the 21143 is in 100-Mb/s SYM mode (CSR6<18>=1) and equals 0 when the 21143 is in 10BASE-T/AUI mode (CSR6<18>=0).
int_l
O/D
15
irdy_l
I/O
51
mii_crs/sd
I
117
mii_dv
I
129
mii_mdc
O
134
mii_mdio mii/sym_rclk
I/O I
135 128
mii_rx_err/ sel10_100
I/O
127
12
Preliminary Datasheet
21143
Table 4. Functional Description of 21143 Signals (Sheet 4 of 6)
Signal mii/ sym_rxd<3:0> mii/sym_tclk mii/ sym_txd<3:0> Type I Pin Number 130, 131, 132,133, 124 119, 120, 121, 122 Description Four parallel receive data lines. This data is driven by an external PHY that attached the media and should be synchronized with the mii_rclk signal. Supports the 25-MHz or 2.5-MHz transmit clock supplied by the external PMD device. This clock should always be active. Four parallel transmit data lines. This data is synchronized to the assertion of the mii_tclk signal and is latched by the external PHY on the rising edge of the mii_tclk signal. In MII mode (CSR6<18>=1, CSR6<23>=0), this pin functions as transmit enable. It indicates that a transmission is active on the MII port to an external PHY device. O 123 In SYM mode, this pin functions as transmit data. This line along with the four data transmit lines (sym_txd<3:0>) provides five parallel data lines in symbol form. The data is synchronized to the rising edge of the sym_tclk signal. Parity is calculated by the 21143 as an even parity bit for the 32-bit ad and 4-bit c_be_l lines. par I/O 59 During address and data phases, parity is calculated on all the ad and c_be_l lines whether or not any of these lines carry meaningful information. The clock provides the timing for the 21143 related PCI bus transactions. All the bus signals are sampled on the rising edge of pci_clk. The supported range of the clock frequency is 20 MHz to 33 MHz. Parity error asserts when a data parity error is detected. The 21143 asserts perr_l when a data parity error is detected in either a master-read or a slave-write operation. perr_l I/O 57 When the 21143 is the bus master and a parity error is detected, the 21143 asserts both CSR5 bit 13 (fatal bus error) and CFCS bit 24 (data parity report). Next, it completes the current data burst transaction, then stops operation. After the host clears the fatal error bit in CSR5, the 21143 continues its operation. Bus request is asserted by the 21143 to indicate to the bus arbiter that it wants to use the bus. Resets the 21143 to its initial state. This signal must be asserted for at least 10 active PCI clock cycles. When in the reset state, all PCI output pins are put into tristate and all PCI O/D signals are floated. If an address parity error is detected and CFCS bit 8 (serr_l enable) is enabled, 21143 asserts both serr_l (system error) and CFCS bit 30 (signal system error). When an address parity error is detected, system error asserts two clocks after the failing address. sr_ck sr_cs sr_di sr_do O O O I 114 115 113 112 Serial ROM clock signal. This pin provides a serial clock output for the serial ROM. Serial ROM chip-select signal. This pin provides a chip select for the serial ROM. Serial ROM data-in signal. This pin serially shifts the write data from the 21143 to the serial ROM device. Serial ROM data-out signal. This pin serially shifts the read data from the serial ROM device to the 21143.
I
O
mii_txen/ sym_txd<4>
pci_clk
I
19
req_l
O
22
rst_l
I
16
serr_l
O/D
58
Preliminary Datasheet
13
21143
Table 4. Functional Description of 21143 Signals (Sheet 5 of 6)
Signal Type Pin Number Description Stop indicator indicates that the current target is requesting the bus master to stop the current transaction. The 21143 responds to the assertion of stop_l when it is the bus master, either to disconnect, retry, or abort. JTAG clock shifts state information and test data into and out of the 21143 during JTAG test operations. If the JTAG port is unused, this pin should be connected to vss. tdi tdo tms tp_rd- tp_rd+ I O I I I 13 14 12 10 9 JTAG data in is used to serially shift test data and instructions into the 21143 during JTAG test operations. JTAG data out is used to serially shift test data out of the 21143 during JTAG test operations. JTAG test mode select controls the state operation of JTAG testing in the 21143. Twisted-pair negative differential receive data from the twisted-pair lines. Twisted-pair positive differential receive data from the twisted-pair lines. Twisted-pair negative differential transmit data. The positive and negative differential transmit data outputs are combined resistively outside the 21143 with equalization to compensate for intersymbol interference on the twisted-pair medium. Twisted-pair positive differential transmit data. The positive and negative differential transmit data outputs are combined resistively outside the 21143 with equalization to compensate for intersymbol interference on the twisted-pair medium. Target ready indicates the target agent's ability to complete the current data phase of the transaction. A data phase is completed on any clock when both trdy_l and irdy_l are asserted. Wait cycles are inserted until both irdy_l and trdy_l are asserted together. When the 21143 is the bus master, target ready is asserted by the bus slave on the read operation, which indicates that valid data is present on the ad lines. During a write cycle, it indicates that the target is prepared to accept data. vcap_h I 110 1, 2, 8, 18, 26, 36, 37, 46, 54, 67, 72, 73, 79, 95, 107, 125, 136, 141 109, 111 Capacitor input for analog phase-locked loop logic. 3.3-V supply input. These pins should be connected to the auxiliary power, if such power exists. Otherwise, these pins should be connected to the main power. Supplies +3.3-V input for analog phase-locked loop logic. Supplies +5-V or +3.3-V reference for clamp logic. vdd_clamp P 20 This pin is also used to identify the lack of main power when the auxiliary power is on. This pin should be connected to the main power.
stop_l
I/O
56
tck
I
11
tp_td- tp_td- -
O O
5 4
tp_td+ tp_td+ +
O O
6 7
trdy_l
I/O
52
vdd
P
vddac
P
vss
P
3, 17, 30, 35, 38, 42, 53, 63, 71, 74, 83, 94, 104, 116, 126, 144 106
Ground pins.
xtal1
I
20-MHz crystal input, or crystal oscillator input.This pin should always be provided with a clock.
14
Preliminary Datasheet
21143
Table 4. Functional Description of 21143 Signals (Sheet 6 of 6)
Signal xtal2 Type O Pin Number 105 Description Crystal feedback output pin used for crystal connections only. If this pin is unused, then it should be unconnected.
2.3
Pin Tables
This section contains four types of pin tables:
* * * *
Table 5 lists the input pins. Table 6 lists the output pins. Table 7 lists the input/output pins. Table 8 lists the open drain pins. Table 5. Input Pins
Signal Active Level Low High -- -- Low High -- High for mii_clsn, -- for sym_rxd<4> High High -- -- Signal mii/sym_tclk pci_clk rst_l sr_do tck tdi tms tp_rd- tp_rd+ vcap_h xtal1 -- Active Level -- -- Low -- -- -- -- -- -- -- -- --
aui_cd- aui_cd+ aui_rd- aui_rd+ gnt_l idsel iref mii_clsn/sym_rxd<4> mii_crs/sd mii_dv mii/sym_rclk mii/sym_rxd<3:0>
Table 6. Output Pins
Signal aui_td- aui_td+ br_a<1> br_ce_l mii_mdc mii/sym_txd<3:0> mii_txen/sym_txd<4> req_l sr_ck Active Level -- -- High Low -- -- High for mii_txen, -- for sym_txd<4> Low -- Signal sr_cs sr_di tdo tp_td- tp_td- - tp_td+ tp_td+ + xtal2 -- Active Level High -- -- -- -- -- -- -- --
Preliminary Datasheet
15
21143
Table 7. Input/Output Pins
Signal Active Level Signal Active Level -- for gep<2>, high for rcv_match, a -- for wake -- for gep<3>, high for link Low -- High for mii_rx_err, -- for sel10_100 devsel_l frame_l gep<0>/aui_bnc gep<1>/activ Low Low -- -- for gep<1>, high for activ par perr_l stop_l trdy_l -- Low Low Low
ad<31:0>
--
gep<2>/rcv_match/wake
br_a<0>/cb_pads_l br_ad<7:0> clkrun_l c_be_l<3:0>
High for br_a<0>, low for cb_pads_l -- Low Low
gep<3>/link irdy_l mii_mdio mii_rx_err/sel10_100
a. The active level is controlled by bit MiscHwOptions<1> (PME_STSCHG) in the serial ROM.
Table 8. Open Drain Pins
Signal int_l Active Level Low serr_l Signal Active Level Low
16
Preliminary Datasheet
21143
2.4
.
Signal Grouping by Function
Table 9 lists the signals according to their interface function. Table 9. Signal Functions (Sheet 1 of 2)
Interface Function Address and data Arbitration Bus command and byte enable Device select Error reporting PCI/CardBus Interrupt System Control signals Power-management status Clock status Pad select Transmit data lines Receive data lines Transmit, receive clocks Transmit enable Collision detect MII error reporting MII/SYM network port Data control MII management data clock MII management data input/output Signal detection SYM mode data lines SYM mode 10/100 select Test access port Serial ROM port Boot ROM port Power JTAG test operations Serial ROM ROM interface 3.3-V or 5.0-V supply input 3.3-V supply input Ground General-purpose pins General-purpose port and LEDs LED indicators 10BASE5/10BASE2 select ad<31:0>, par gnt_l, req_l c_be_l<3:0> devsel_l, idsel perr_l, serr_l int_l pci_clk, rst_l frame_l, stop_l, irdy_l, trdy_l wake clkrun_l cb_pads_l mii/sym_txd<3:0> mii/sym_rxd<3:0> mii/sym_tclk, mii/sym_rclk mii_txen mii_clsn mii_rx_err mii_dv, mii_crs mii_mdc mii_mdio sd sym_rxd<4>, sym_txd<4> sel10_100 tck, tdi, tdo, tms sr_ck, sr_cs, sr_di, sr_do br_a<1:0>, br_ad<7:0>, br_ce_l vdd_clamp vdd, vddac vss gep<3:0> activ, rcv_match, link aui_bnc Signals
Preliminary Datasheet
17
21143
Table 9. Signal Functions (Sheet 2 of 2)
Interface Function Analog phase-locked loop logic AUI collision data Network connection AUI transmit and receive data Crystal oscillator Twisted-pair transmit and receive data iref, vcap_h aui_cd-, aui_cd+ aui_rd-, aui_rd+, aui_td-, aui_td+ xtal1, xtal2 tp_rd-, tp_rd+, tp_td-, tp_td- -, tp_td+, tp_td+ + Signals
18
Preliminary Datasheet
21143
3.0
Electrical and Environmental Specifications
This section contains the electrical and environmental specifications for the 21143.
Caution:
Stresses greater than the maximum or less than the minimum ratings can cause permanent damage to the 21143. Exposure to the maximum or minimum ratings for extended periods of time lessen the reliability of the 21143.
3.1
.
Voltage Limit Ratings
Table 10 lists the voltage limit ratings. Table 10. Voltage Limit Ratings
Parameter Power supply voltage vdd_clamp (5.0 V) vdd_clamp (3.3 V)
1
Minimum 3.0 V 4.75 V 3.0 V --
Maximum 3.6 V 5.25 V 3.6 V 2000 V
ESD protection voltage
1.
In the 3.3-V signaling environment, vdd_clamp must not be greater than vdd + 0.3 V.
3.2
.
Temperature Limit Ratings
Table 11 lists the temperature limit ratings. Table 11. Temperature Limit Ratings
Parameter Storage temperature Operating temperature Minimum -55C (-67F) 0C (32F) Maximum 125C (257F) 70C (158F)
Preliminary Datasheet
19
21143
3.3
Power Specifications
The values in Table 12 are based on a PCI or CardBus* clock frequency of 33 MHz and a network data rate of 10/100 Mb/s for MII for legacy power-saving modes.
Table 12. Legacy Power-Saving Modes Specification
Mode After power-up Normal Snooze Sleep
1. 2.
IDD1 (mA) 54 150 85 25
Power1 (mW) 178 495 280 82
IDD2(mA) -- 230 145 115
Power2 (mW) -- 828 522 414
Typical: vdd = 3.3 V, Ta = 25C Maximum: vdd = 3.6 V, Ta = 0C
The values in Table 13 are based on a PCI clock frequency of 25 MHz, vdd at 3.3 V, Ta at 25C, and a network data rate of 10/100 Mb/s for ACPI modes. Table 13. ACPI Modes Power Specification
Condition D0 normal, full network activity D0 snooze, 50% network activity D1 snooze, 50% network activity D2 snooze, PCI clock running D3 snooze, PCI clock stopped After power-up, CardBus pads IDD (mA) 145 mA 130 mA 118 mA 109 mA 102 mA 51 mA Typical Power Consumption (mW) 479 mW 429 mW 389 mW 356 mW 337 mW 168 mW
3.4
PCI Bus and CardBus Electrical Parameters
This section describes the PCI Bus and CardBus characteristics for the 21143.
20
Preliminary Datasheet
21143
3.4.1
.
PCI and CardBus I/O Voltage Specifications
The 21143 meets the I/O voltage specifications listed in Table 14 and Table 15. Table 14. I/O Voltage Specifications for 5.0-V Levels
Symbol Vih Vil Ii
1
Parameter Input high voltage Input low voltage Input leakage current Output high voltage Output low voltage
Condition -- -- 0.5 VMinimum 2.0 V -0.5 V -- 2.4 V -- 5 pF
Maximum vdd_clamp + 0.5 V 0.8 V 10 A -- 0.55 V 8 pF
Voh Vol
2 3
Cap
1. 2. 3.
Pin capacitance
Input leakage currents include high-impedance output leakage for all bidirectional buffers with tristate outputs. Signals without pull-up resistors must have 3-mA low output current. Signals requiring pull-up resistors (including frame_l, trdy_l, irdy_l, devsel_l, stop_l, serr_l, and perr_l) must have 6 mA. Parameter design guarantee.
Table 15. I/O Voltage Specifications for 3.3-V Levels
Symbol Vih Vil Ii
1
Parameter Input high voltage Input low voltage Input leakage current Output high voltage Output low voltage Pin capacitance
Condition -- -- 0.0 VMinimum 0.475*vdd_clamp -0.5 V -- 0.9*vdd_clamp -- 5 pF
Maximum vdd_clamp + 0.5 V 0.325*vdd_clamp 70 A -- 0.1*vdd_clamp 8 pF
Voh Vol Cap2
1. 2.
Input leakage currents include high-impedance output leakage for all bidirectional buffers with tristate outputs. Parameter design guarantee.
Preliminary Datasheet
21
21143
3.4.2
System Bus Reset
System bus (PCI or CardBus) reset (rst_l) is an asynchronous signal that must be active for at least 10 system bus (PCI or CardBus) clock (pci_clk) cycles. Figure 3 shows the reset timing characteristics, and Table 16 lists the reset signal limits.
pci_clk
rst_l
10 pci_clk Cycles
Internal Reset 33 pci_clk Cycles
A5477-01
Figure 3. Reset Timing Diagram Table 16. Reset Timing Parameters
Symbol Trst Parameter rst_l pulse width Minimum 10*pci_clk Maximum Not applicable Condition pci_clk active
3.4.3
PCI and CardBus Clock Specifications
The clock frequency range1 for PCI and CardBus is between 20 MHz and 33 MHz. Figure 4 shows the PCI and CardBus clock specification timing characteristics and the required measurement points for both the 5.0-V and 3.3-V signaling environments. Table 17 lists the frequency-derived clock specifications.
1. The PCI and CardBus clock frequency is from dc to 33 MHz; network operational with the PCI or CardBus clock from 20 MHz to 33 MHz.
22
Preliminary Datasheet
21143
5.0-V Clock
2.0 V
Thigh
Tlow 0.8 V
3.3-V Clock
0.475 * vdd_clamp 0.325 * vdd_clamp
Tr
Tf
Tcycle
LJ03910A.AI4
Figure 4. PCI and CardBus Clock Specification Timing Diagram
Table 17. PCI and CardBus Clock Timing Specifications
Symbol Tcycle Thigh Tlow Tr/Tf1
1.
Parameter Cycle time pci_clk high time pci_clk low time pci_clk slew rate
Minimum 30 ns 11 ns 11 ns 1 V/ns
Maximum 50 ns -- -- 4 V/ns
Rise and fall times are specified in terms of the edge rate measured in V/ns. Parameter design guarantee.
Preliminary Datasheet
23
21143
3.4.4
Other PCI and CardBus Signals
Figure 5 shows the timing diagram characteristics for other PCI and CardBus signals and Table 18 lists their timing specifications. This timing is identical to the timing for the general-purpose register signals.
Vtest Clk
1
Tval (max)
Tval (min)
Output
Ton Input
Toff
1
Th Tsu Vtest is 1.5 V in a 5.0-V signaling environment and is 0.4 * vdd_clamp in a 3.3-V signaling environment.
LJ04719A.AI4
Figure 5. Timing Diagram for Other PCI and CardBus Signals
Table 18. Other PCI and CardBus Signals' Timing Specifications
Symbol Tval Ton Toff
1
Parameter clk-to-signal valid delay
2 3
Minimum 2 ns 2 ns -- 7 ns 0 ns 1 V/ns 0.25 V/ns
Maximum 11 ns -- 28 ns -- -- 4 V/ns 1 V/ns
1
Float-to-active delay from clk Active-to-float delay from clk
4
Tsu4 Th Slewr, Slewf Slewr, Slewf
1. 2. 3. 4. 5. 6.
Input signal valid setup time before clk Input signal hold time from clk
4 4
Output rise and fall slew rate Output rise and fall slew rate
5 6
Load for this measurement is as specified in PCI Local Bus Specification, Revision 2.0 and PCI Local Bus Specification, Revision 2.1. Valid delays for PCI, selected by default when pin cb_pad_l is not pulled down externally. Valid delays for CardBus, selected by default when pin cb_pad_l is pulled down externally. Parameter design guarantee. Slew rate for PCI, selected by default when pin cb_pad_l is not pulled down externally. Slew rate for CardBus, selected when pin cb_pad_l is pulled down externally.
24
Preliminary Datasheet
21143
3.5
.
AUI and Twisted-Pair DC Specifications
Table 19 lists the dc specifications for the AUI and twisted-pair parts of the SIA. Table 19. AUI and Twisted-Pair DC Specifications
Symbol AUI Pins Vod Vodi1 Iodi1 Vasq+1 Vasq-1 Vodu1 Transmit differential output voltage (aui_td) Transmit differential output idle voltage (aui_td) Transmit differential output idle current (aui_td) Differential positive squelch threshold (aui_rd) Differential negative squelch threshold (aui_rd and aui_cd) Transmit differential output undershoot voltage on return to zero (aui_td) 78 termination 78 termination 78 termination -- -- 78 termination 550 -40 -1 175 -275 1200 +40 +1 275 -175 mV mV mA mV mV Definition Condition Minimum Maximum Unit
--
-100
mV
Twisted-Pair Interface Pins Vtoh Vtol Vtsq+1 Vtsq-1 Vtdif1
1.
Output high voltage (tp_td and tp_td) Output low voltage (tp_td and tp_td) Differential positive squelch threshold (tp_rd) Differential negative squelch threshold (tp_rd) Differential input voltage range (tp_rd)
Ioh = -25 mA Iol = 25 mA -- -- --
2.5 -- 300 -520 -3.1
-- 0.5 520 -300 3.1
V V mV mV V
Parameter design guarantee.
Preliminary Datasheet
25
21143
3.6
Serial Interface Attachment Specifications
This section describes the dc specifications and timing limits of the SIA unit.
3.6.1
Serial Clock Timing
Figure 6 shows the serial clock (TTL or CMOS) timing characteristics, and Table 20 lists the serial clock timing specifications.
Tch
Tcl
Tcr Tcycle
Tcf
LJ-04101.AI4
Figure 6. Serial Clock (XTAL) Timing Diagram Table 20. Serial Clock (XTAL) Timing Specifications
Symbol Tcr1 Tcf1 Tcycle Tch Tcl
1.
Parameter Rise time Fall time
Minimum -- -- 49.995 ns 0.4*Tcycle 0.4*Tcycle
Maximum 4 ns 4 ns 50.005 ns 0.6*Tcycle 0.6*Tcycle
1
Cycle time Clock high time Clock low time
Parameter design guarantee.
26
Preliminary Datasheet
21143
3.6.2
Internal SIA Mode AUI Timing--Transmit
Figure 7 shows the internal SIA transmit timing characteristics for the AUI, and Table 21 lists the internal SIA transmit timing limits for the AUI.
1
0
1
1
ETD (End Transmit Delimiter)
xtal1 Tatp Tatr aui_td+
Tatf
Tate
aui_tdML11428A.AI4
Figure 7. Internal SIA Mode AUI Timing Diagram--Transmit
Table 21. Internal SIA Mode AUI Timing Specifications--Transmit
Symbol Tatp Tatr1 Tatf
1
Definition aui_td+, aui_td- propagation delay from xtal1 fall aui_td+, aui_td- rise time aui_td+, aui_td- fall time aui_td+, aui_td- rise and fall time mismatch (not shown) aui_td end transmit delimiter length
Minimum -- 2 2 -- 345
Maximum 30 8 8 1 405
Unit ns ns ns ns ns
Tatm1 Tate1
1.
Parameter design guarantee.
Preliminary Datasheet
27
21143
3.6.3
Internal SIA Mode AUI Timing--Receive
Figure 8 shows the internal SIA receive timing characteristics for the AUI, and Table 22 lists the internal SIA receive timing limits for the AUI.
Tudm Tudf Vasq+ VasqTudo Tudm A5994-01
Figure 8. Internal SIA Mode AUI Timing Diagram--Receive
3.6.4
Internal SIA Mode AUI Timing--Collision
Figure 9 shows the internal SIA collision timing characteristics for the AUI, and Table 22 lists the internal SIA collision timing limits for the AUI.
Tucf
aui_cd+/Tuco Tucm
Vasq-
MLO10338.AI4
Figure 9. Internal SIA Mode AUI Timing Diagram--Collision Table 22. Internal SIA Mode AUI Timing Specifications--Receive and Collision
Symbol Tudo Tudm1 Tudf1 Tuco Tucm1 Tucf1
1.
Definition aui_rd start of frame pulse width aui_rd delay between opposite squelch crossings not recognized as end of packet aui_rd delay from last squelch crossing recognized as end of packet aui_cd start of collision pulse width aui_cd delay between squelch crossings not recognized as end of collision aui_cd delay from last squelch crossing recognized as end of collision
Minimum 15 -- 150 20 -- 150
Maximum 20 140 -- 25 140 --
Unit ns ns ns ns ns ns
Parameter design guarantee.
28
Preliminary Datasheet
21143
3.6.5
Internal SIA Mode 10BASE-T Interface Timing--Transmit
Figure 10 shows the internal SIA transmit timing characteristics for the 10BASE-T interface, and Table 23 lists the internal SIA transmit limits.
1 0 1 1 ETD (End Transmit Delimiter)
xtal1 Tpdp Tpdr tp_td+
Tpdf
Tped
Tpdc tp_td--
Tpen
tp_td-
Tpdc tp_td++
ML11429A AI4
Figure 10. Internal SIA Mode 10BASE-T Interface Timing Diagram-- Transmit
t
Table 23. Internal SIA Mode 10BASE-T Interface Timing Specifications--Transmit
Symbol Tpdp Tpdr
1
Definition tp_td+, tp_td- propagation delay from xtal1 fall tp_td+, tp_td++, tp_td-, tp_td- - rise time tp_td+, tp_td++, tp_td-, tp_td- - fall time tp_td+, tp_td++, tp_td-, tp_td- - rise and fall time mismatch (not shown) tp_td+ to tp_td- - and tp_td- to tp_td++ delay tp_td end transmit delimiter length tp_td++/- - end transmit delimiter length
Minimum -- 2 2 -- 46 295 245
Maximum 30 8 8 1 54 355 305
Unit ns ns ns ns ns ns ns
Tpdf1 Tpdm1 Tpdc1 Tped Tpen
1.
1 1
Parameter design guarantee.
Preliminary Datasheet
29
21143
3.6.6
Internal SIA Mode 10BASE-T Interface Timing--Receive
Figure 11 shows the internal SIA receive timing characteristics for the 10BASE-T interface, and Table 24 lists the internal SIA receive limits for the 10BASE-T interface.
Tsf Tsn
Tsf Tsn Tdm Tdf Vtsq+ Vtsq-
tp_rd+/Tsn Tsf Tsf Tsn Tsf Tsn Tdm
A5478-01
Figure 11. Internal SIA Mode 10BASE-T Interface Timing Diagram-- Receive
Table 24. Internal SIA Mode 10BASE-T Interface Timing Specifications--Receive
Symbol Tsn1 Tsf1 Tdm1 Tdf1
1.
Definition tp_rd start of frame pulse width during smart squelch operation tp_rd maximum delay between opposite squelch crossings not to turn smart squelch off tp_rd delay between opposite squelch crossings not recognized as end of packet tp_rd delay from last squelch crossing recognized as end of packet
Minimum 15 140 -- 150
Maximum 20 150 140 --
Unit ns ns ns ns
Parameter design guarantee.
30
Preliminary Datasheet
21143
3.6.7
Internal SIA Mode 10BASE-T Interface Timing--Idle Link Pulse
Figure 12 shows the internal SIA idle link pulse timing characteristics for the 10BASE-T interface, and Table 25 lists the internal SIA idle link pulse limits for the 10BASE-T interface.
tp_td+ Tpld Tplp
tp_td++ Tplc
tp_td-
Tplc
tp_td-MLO10341.AI4
Figure 12. Internal SIA Mode 10BASE-T Interface Timing Diagram--Idle Link Pulse
Table 25. Internal SIA Mode 10BASE-T Interface Timing Specifications--Idle Link Pulse
Symbol Tpld1 Tplc1 Tplp1
1.
Definition tp_td+ idle link pulse width tp_td++ and tp_td- - idle link pulse width Idle link pulse period
Minimum 80 40 8
Maximum 120 60 24
Unit ns ns ms
Parameter design guarantee.
Preliminary Datasheet
31
21143
3.7
MII Interface Specifications
Table 26 lists the specifications for the MII interface. Table 26. MII Interface
Symbol Voh Vol Vih Vil Iin Ioz Definition Output high voltage Output low voltage Input high voltage Input low voltage Input current Maximum tristate output leakage current Condition Ioh = -4 mA Iol = 4 mA -- -- Vin = vcc or vss Vin = vdd or vss Minimum 2.4 -- 2.0 -- -10.0 -10.0 Maximum -- 0.4 -- 0.8 10.0 10.0 Unit V V V V A A
3.8
MII/SYM Port Timing
This section describes the MII/SYM port timing limits.
3.8.1
MII/SYM 10/100-Mb/s and 10-Mb/s Timing--Transmit
Figure 13 shows the MII/SYM port transmit timing characteristics, and Table 27 lists the MII/SYM port transmit timing limits.
32
Preliminary Datasheet
21143
Tcc Tcr Tch mii/sym_tclk Tcf Tcl 2 3 4 5
1 Trv
mii/sym_txd<3:0> Trh mii_txen
LJ-04944.AI4
Figure 13. MII/SYM Port Timing Diagram--Transmit
Table 27. MII/SYM Port Timing Limits--Transmit
Symbol Tcc1 Tch Tcl Tcr
3
Definition mii/sym_tclk cycle mii/sym_tclk high time mii/sym_tclk low time mii/sym_tclk rise time mii/sym_tclk fall time mii_tclk rise to mii_txen valid time or mii/sym_tclk rise to mii/sym_txd valid time mii_txen hold after mii_tclk rise time
Minimum -- 14t 14t -- -- --
2 2
Typical 40t2 -- -- 8 8 --
Maximum -- 26t 26t -- -- 20
2 2
Unit ns ns ns ns ns ns
Tcf3 Trv4
Trh
1. 2. 3. 4.
5
--
--
ns
50 parts per million. t=1 for 100-Mb/s operation; t=10 for 10-Mb/s operation. Parameter design guarantee. The transmit data (mii/sym_txd) and transmit enable (mii_txen) output pins are driven internally from the rising edge of mii/sym_tclk.
Preliminary Datasheet
33
21143
3.8.2
MII/SYM 10/100-Mb/s Timing--Receive
Figure 14 shows the MII/SYM port receive timing characteristics, and Table 28 lists the MII/SYM port receive timing limits.
Tcc Tcr Tch mii/sym_rclk Tts mii/sym_rxd<3:0> Tth Tcf Tcl
mii_dv
LJ-04998.AI4
Figure 14. MII/SYM Port Timing Diagram--Receive
Table 28. MII/SYM Port Timing Limits--Receive
Symbol Tcc Tc Tcl Tcr3 Tcf3 Tts4
1
Definition mii/sym_rclk cycle time mii/sym_rclk high time mii/sym_rclk low time mii/sym_rclk rise time mii/sym_rclk fall time mii/sym_rxd setup (both rise and fall transactions) to mii/sym_rclk rise time or mii_dv setup (both rise and fall transactions) to mii_rclk rise time mii/sym_rxd hold (both rise and fall transactions) after mii/sym_rclk rise time or mii_dv hold (both rise and fall transactions) after mii_rclk rise time
Minimum -- 14t 14t -- --
2 2
Typical 40t
2
Maximum -- 26t 26t -- --
2 2
Unit ns ns ns ns ns
-- -- 8 8
8
--
--
ns
Tth
10
--
--
ns
1. 2. 3. 4.
50 parts per million. t=1 for 100-Mb/s operation; t=10 for 10-Mb/s operation. Parameter design guarantee. The receive data (mii/sym_rxd) and data valid (mii_dv) input pins are latched internally on the rising edge of mii/ sym_rclk.
34
Preliminary Datasheet
21143
3.8.3
SYM 10/100-Mb/s Timing--Signal Detect
Figure 15 shows the SYM port signal detect timing characteristics, and Table 29 lists the SYM port signal detect timing limits.
sym_rclk
1
2 Tts
3 Tth
4
5
sd
LJ-04945.AI4
Figure 15. SYM Port Timing Diagram--Signal Detect
Table 29. SYM Port Timing Limits--Signal Detect
Symbol Tts1 Tth1
1.
Definition sd setup (both rise and fall transactions) to sym_rclk fall time sd hold (both rise and fall transactions) after sym_rclk fall time
Minimum 10 12
Maximum -- --
Units ns ns
Input signal detect (sd) is latched internally on the falling edge of sym_rclk.
3.8.4
MII 10/100-Mb/s Timing--Receive Error
Figure 16 shows the MII port receive error timing characteristics, and Table 30 lists the MII port receive error timing limits.
mii_rclk
1
2 Tts
3
4 Tth
5
mii_rx_err
LJ03906A.AI4
Figure 16. MII Port Timing Diagram--Receive Error
Table 30. MII Port Timing Limits--Receive Error
Symbol Tts1 Tth1
1.
Definition mii_rx_err setup (both rise and fall transactions) to mii_rclk rise time mii_rx_err hold (both rise and fall transactions) after mii_rclk rise time
Minimum 10 10
Maximum -- --
Unit ns ns
Input signal detect (mii_rx_err) is latched internally on the falling edge of mii_rclk.
Preliminary Datasheet
35
21143
3.8.5
MII 10/100-Mb/s Timing--Carrier Sense and Collision
Figure 17 shows the MII port carrier sense and collision timing characteristics, and Table 31 lists the MII port carrier sense and collision timing limits.
mii_clsn mii_crs
Tclh
LJ-03929.AI4
Figure 17. MII Port Timing Diagram--Carrier Sense and Collision Table 31. MII Port Timing Limits--Carrier Sense and Collision
Symbol Tclh Definition mii_crs, mii_clsn high time Minimum 20 Maximum -- Unit ns
3.9
Boot ROM and Serial ROM Port Specification
Table 32 lists the dc specifications for the boot ROM and serial ROM ports. These specifications apply in any mode in which the ports are used. Table 32. Boot ROM and Serial ROM Port DC Specifications
Symbol Voh Vol Vih Vil Ioz1
1.
Definition Output high voltage Output low voltage Input high voltage Input low voltage Maximum tristate output leakage current
Condition Ioh = -4 mA Iol = 4 mA -- -- Vout = vdd or vss
Minimum 2.4 -- 2.0 -- -10
Maximum -- 0.4 -- 0.8 10
Unit V V V V A
For sr_do and br_ce_l, the maximum value is 1000.0 mA.
36
Preliminary Datasheet
21143
3.10
Boot ROM Port Timing
This section describes the boot ROM port timing.
3.10.1
Boot ROM Read Timing
Figure 18 shows the boot ROM read timing characteristics, and Table 33 lists the boot ROM read timing limits.
Tads
Tadh
Tads
Tadh
Tavqv
br_ad<7:0>
Address = <7:2> oe = O, we = 1
Address <15:8>
Data <7:0> Valid
br_a<1>
Address <1>
br_a<0> br_ce_l
Address <17>
Address <16>
Address <0>
Telqx Telqv
Toh Tehqz Tavav A5993-01
Figure 18. Boot ROM Read Timing Diagram Table 33. Boot ROM Read Timing Specifications
Symbol Tavav Tavqv Telqv Telqx
1
Parameter Read cycle time Address to output delay br_ce_l to output delay br_ce_l to output low impedance br_ce_l going high to output high impedance Output hold from br_ce_l change Address setup to latch enable high Address hold from latch enable high
Minimum 240 -- -- 0 -- 0 30 30
Maximum -- 240 240 -- 55 -- -- --
Unit ns ns ns ns ns ns ns ns
Tehqz1 Toh Tads Tadh
1.
Parameter design guarantee.
Preliminary Datasheet
37
21143
3.10.2
Boot ROM Write Timing
Figure 19 shows the boot ROM write timing characteristics, and Table 34 lists the boot ROM write timing limits.
Tads
Tadh
Tads
Tadh Data<7:0>
br_ad<7:0>
Address=<7:2> oe = 1, we = 0
Address<15:8>
br_a<1>
Address<1>
br_a<0>
Address<17>
Address<16>
Address<0>
br_ce_l
Teleh Tehax Tehdx
Tdveh Taveh Tavav
A5479-01
Figure 19. Boot ROM Write Timing Diagram Table 34. Boot ROM Write Timing Specifications
Symbol1 Tavav Teleh Taveh Tdveh Tehdx Tehax Tads Tadh
1.
Parameter Write cycle time br_ce_l pulse width Address setup to br_ce_l going high Data setup to br_ce_l going high Data hold from br_ce_l going high Address hold from br_ce_l high Address setup to latch enable high Address hold from latch enable high
Minimum 240 70 50 50 10 15 30 30
Unit ns ns ns ns ns ns ns ns
There are no maximum specifications.
38
Preliminary Datasheet
21143
3.11
Serial ROM Port Timing
Figure 20 shows the serial ROM port timing, and Table 35 lists the characteristics. This timing is identical to the timing for the MII management signals (mii_mdio and mii_mdc).
sr_cs, sr_ck, sr_di, sr_do
Tsr
Tsf
LJ-03909.AI4
Figure 20. Serial ROM Port Timing Diagram Table 35. Serial ROM Port Timing Characteristics
Symbol Tsr1 Tsf1
1.
Definition Rise time Fall time
Minimum -- --
Maximum 10 10
Unit ns ns
Parameter design guarantee.
3.12
External Register Timing
Figure 21 shows the external register read timing characteristics, and Figure 22 shows the write timing characteristics. Table 36 lists the external register timing specifications for both read and write operations.
br_ad<7:0>
DataValid
br_a<0>
br_ce_l Tpd Tehqz
LJ-05000.AI4
Figure 21. External Register Read Timing Diagram
Preliminary Datasheet
39
21143
br_ad<7:0>
Data<7:0>
br_a<0>
br_ce_l Teleh Ts Th
LJ-05001.AI4
Figure 22. External Register Write Timing Diagram Table 36. External Register Timing Specifications
Symbol Teleh Read Timing Tpd Tehqz
1
Parameter br_ce_l pulse width
Minimum 240
Maximum --
Unit ns
br_ce_l low to br_ad<7:0> valid high br_ce_l high to br_ad<7:0> high impedance
-- --
20 20
ns ns
Write Timing Ts Th
1.
Data setup time prior to br_ce_l Data hold after br_ce_l high
30 30
-- --
ns ns
Parameter design guarantee.
40
Preliminary Datasheet
21143
3.13
Joint Test Action Group--Test Access Port
This section provides the joint test action group (JTAG) test access port specifications.
3.13.1
.
JTAG DC Specifications
Table 37 lists the dc specifications for the JTAG pins Table 37. JTAG DC Specifications
Symbol Voh Vol Vih Vil Iip Ioz
1.
Definition Output high voltage Output low voltage Input high voltage Input low voltage Input leakage current on pins with internal pull-ups (tdi and tms) Tristate output leakage current (tdo)
Condition Ioh = -4 mA Iol = 4 mA -- -- 0.0Minimum 2.4 -- 2.0 -- --
Maximum -- 0.4 -- 0.8 +20/-10001
Unit V V V V A A
--
20
For pins tdi and tms that have internal pull-ups, the leakage current can get to 1.0 mA when Vin = 0 V.
Preliminary Datasheet
41
21143
3.13.2
JTAG Boundary-Scan Timing
Figure 23 shows the JTAG boundary-scan timing, and Table 38 lists the interface signal timing relationships.
Tck_cycle Tck_f
tck
Tck_r
Tms_s
Tms_h
tms
Tdi_s
Tdi_h
tdi Tdo_d
tdo
LJ-03908.AI4
Figure 23. JTAG Boundary-Scan Timing Diagram Table 38. JTAG Interface Signal Timing Relationships
Symbol Tms_s Tms_h Tdi_s Tdi_h Tdo_d Tck_r Tck_f
1
Parameter tms setup time tms hold time tdi setup time tdi hold time tdo delay time tck rise time tck fall time tck cycle time
Minimum 20 5 20 5 -- -- -- 90
Maximum -- -- -- -- 20 3 3 --
Unit ns ns ns ns ns ns ns ns
1
Tck_cycle
1.
Parameter design guarantee.
42
Preliminary Datasheet
21143
4.0
Mechanical Specifications
The 21143 is contained in either a 144-pin LQFP package type or a 144-pin MQFP package type. Figure 24 shows the mechanical layout of the LQFP, and Table 39 lists the LQFP package dimensions in millimeters. Figure 25 shows the mechanical layout of the MQFP, and Table 40 lists the MQFP package dimensions in millimeters.
Preliminary Datasheet
43
21143
-AD D1
Pin 1
Detail "A"
Pin # Direction
(A) A2 A1
b
144-Pin LQFP
E1 E
-B-
e
See Detail "A"
A // 0.13 C - H - Datum Plane - C - Seating Plane
ddd M C A
S
B
S
ccc C
R
Notes: All dimensions are in millimeters. - Basic Dimension
L (LL) 0 -7 c
o o
(
) - Reference Dimension
LJ04510A .AI4
Figure 24. 144-Pin LQFP Package
44
Preliminary Datasheet
21143
Table 39. 144-Pin LQFP Package Dimensions
Symbol LL e L A A1 A2 b c ccc ddd D D1 E E1 R
1. 2.
Dimension Lead length Lead pitch Foot length Package overall height Package standoff height Package thickness Lead width Lead thickness Coplanarity Lead skew Package overall width Package width Package overall length Package length Ankle radius
Value (mm) 1.00 reference1 0.50 BSC2 0.45 minimum to 0.75 maximum 1.60 maximum 0.05 minimum 1.35 minimum to 1.45 maximum 0.17 minimum to 0.27 maximum 0.09 minimum to 0.20 maximum 0.08 0.08 22.00 BSC 20.00 BSC 22.00 BSC 20.00 BSC 0.08 minimum to 0.20 maximum
The value for this measurement is for reference only. ANSI Y14.5M-1982 American National Standard Dimensioning and Tolerancing, Section 1.3.2, defines Basic Dimension (BSC) as: A numerical value used to describe the theoretically exact size, profile, orientation, or location of a feature or datum target. It is the basis from which permissible variations are established by tolerances on other dimensions, in notes, or in feature control frames.
Preliminary Datasheet
45
21143
-AD D1
Pin 1
Detail "A"
Pin # Direction
(A) A2 A1
b
144-Pin MQFP
E1 E
-B-
e
See Detail "A"
A // 0.13 C - H - Datum Plane - C - Seating Plane
ddd M C A
S
B
S
ccc C
R
Note: All dimensions are in millimeters. - Basic Dimension
L (LL) 0 -7 c
o o
(
) - Reference Dimension
LJ04510B .AI4
Figure 25. 144-Pin MQFP Package
46
Preliminary Datasheet
21143
Table 40. 144-Pin MQFP Package Dimensions
Symbol LL e L A A1 A2 b c ccc ddd D D1 E E1 R
1. 2.
Dimension Lead length Lead pitch Foot length Package overall height Package standoff height Package thickness Lead width Lead thickness Coplanarity Lead skew Package overall width Package width Package overall length Package length Ankle radius
Value (mm) 1.60 reference1 0.65 BSC2 0.65 minimum to 1.03 maximum 4.1 maximum 0.25 minimum 3.20 minimum to 3.60 maximum 0.22 minimum to 0.40 maximum 0.11 minimum to 0.23 maximum 0.10 0.13 31.20 BSC 28.00 BSC 31.20 BSC 28.00 BSC 0.13 minimum to 0.30 maximum
The value for this measurement is for reference only. ANSI Y14.5M-1982 American National Standard Dimensioning and Tolerancing, Section 1.3.2, defines Basic Dimension (BSC) as: A numerical value used to describe the theoretically exact size, profile, orientation, or location of a feature or datum target. It is the basis from which permissible variations are established by tolerances on other dimensions, in notes, or in feature control frames.
Preliminary Datasheet
47
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Copies of documents that have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-332-2717 or by visiting Intel's website for developers at:
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